Low-power spatial computing using dynamic threshold devices

Asynchronous spatial computing systems exhibit only localized communication, their overall data-flow being controlled by handshaking. It is therefore straightforward to determine when a particular part of such a system is active. We show that using thin-body double-gate fully depleted SOI transistors, the shift in threshold voltage that can be produced by modulating the back-gate bias is sufficient to reduce subthreshold leakage power by a factor of more than 104 in typical circuits. Using TBFDSOI devices in spatial computing architectures will allow overall power to be greatly reduced while maintaining high performance

A polymorphic hardware platform

In the domain of spatial computing, it appears that platforms based on either reconfigurable datapath units or on hybrid microprocessor/logic cell organizations are in the ascendancy as they appear to offer the most efficient means of providing resources across the greatest range of hardware designs. This paper encompasses an initial exploration of an alternative organization. It looks at the effect of using a very fine-grained approach based on a largely undifferentiated logic cell that can be configured to operate as a state element, logic or interconnect - or combinations of all three. A vertical layout style hides the overheads imposed by reconfigurability to an extent where very fine-grained organizations become a viable option. It is demonstrated that the technique can be used to develop building blocks for both synchronous and asynchronous circuits, supporting the development of hybrid architectures such as globally asynchronous, locally synchronous

A low-power reconfigurable logic array based on double-gate transistors

A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate. Each cell in the array can act as logic or interconnect, or both, contrasting with current field-programmable gate array structures in which logic and interconnect are built and configured separately. Simulation results are presented for a fully depleted SOI DG-MOSFET implementation and contrasted with two other proposals from the literature based on directed self-assembly

Why area might reduce power in nanoscale CMOS

In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reduction in VDD which results in a reduction in power. Under a scaling regime which allows threshold voltage to increase as VDD decreases we find that dynamic and subthreshold power loss in CMOS exhibit a dependence on area proportional to A(s-3)s/ while gate leakage power ? A(s-6)s/, and short circuit power ? A(s-8)s/. Thus, with the large number of devices at our disposal we can exploit techniques such as spatial computing, tailoring the program directly to the hardware, to overcome the negative effects of scaling. The value of s describes the effectiveness of the technique for a particular circuit and/or algorithm - for circuits that exhibit a value of s =3, power will be a constant or reducing function of area. We briefly speculate on how s might be influenced by a move to nanoscale technology

Soft error rate estimation in deep sub-micron CMOS

Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions. In this paper, we model the sensitivity of individual circuit classes to single event upsets using predictive technology models over a range of CMOS device sizes from 90 nm down to 32 nm. Modeling the relative position of particle strikes as injected current pulses of varying amplitude and fall time, we find that the critical charge for each technology is an almost linear function both of the fall time of the injected current and the supply voltage. This simple relationship will simplify the task of estimating circuit-level soft error rate (SER) and support the development of an efficient SER modeling and optimization tool that might eventually be integrated into a high level language design flow

A computer aided teleoperator system Final report

Computer aided teleoperator system for remote handling task

High performance extendable instruction set computing

In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. The architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. The offset and immediate operands can be extended to 32 bits via the operation of an extension flag. The code density of the EISC instruction set and its memory transfer erformance is shown to be significantly higher than current architectures making it a suitable candidate for the next generation of embedded computer systems. The compact EISC instruction set introduces data dependencies that seemingly limit deep pipeline and superscalar implementations. This paper suggests a mechanism by which these dependencies might be removed in hardware

“A” for Attitude—Attitudes towards Dyslexia in Higher Education

This paper makes the case for the importance of an empathetic approach to understanding dyslexia, in educational establishments, especially in Higher Education. An awareness of the implications that having dyslexia and how this affects both study skills (concentration, organisation, revision and so forth) and presentation skills (completion of assignments within academic language and structures and without grammar, punctation and spelling errors) is accentuated in this article.This research employs meta-ethnography, the Critical Appraisal Skills Programme (CASP) and a grounded theory overlay to thematic critical analysis. In so doing, UK literature of both quantitative and qualitative format was examined through specifying inclusion criteria and using a filtering approach.The justification for this work is to challenge any institutional or individual indirect discriminatory practice towards students with dyslexia.Conclusions indicate the need for enhanced institutional understanding of dyslexia and associated provision for individual dyslexic learners within Higher Education in its entirety. For example, access to digitalised resources, individual tutorials, assistive technology and adjusted expectations in marking criteria (as not to penalise for issues concomitant with dyslexia)